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Altera_Forum
Honored Contributor
Honored ContributorVHDL std_logic_vector Comparisons
What's the best way to compare std_logic_vector 's to zero in VHDL? I don't want to use conversion functions, create a std_logic_vector of "0"s, or do element-by-element comparisons.
Altera_ForumHonored Contributor
Honored ContributorSure - you can even have record types on the entity.
One problem with integers could mask initialization problems when comparing gate-level simulations with RTL: there is no "X" value for integers. So I try to stick to slv.
