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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL std_logic_vector Comparisons

What's the best way to compare std_logic_vector 's to zero in VHDL? I don't want to use conversion functions, create a std_logic_vector of "0"s, or do element-by-element comparisons.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You can create a std_logic_vector of zeros using "others" that's nice.

constant bus_width : integer := 32;

signal my_signal : std_logic_vector(bus_width -1 downto 0);

constant zeros : std_logic_vector(bus_width -1 downto 0);

zeros <= (others => '0');

...

if (my_signal = zeros) then...

This makes it a little cleaner.