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VHDL's avatar
VHDL
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4 years ago

VHDL simulation using modelsim software

Dear Technical team, Developed test program for switch IC using VHDL and simulated with modelsim software. Result is in the 'Z' state . Kindly support me to solve this issue.. please find the b...
sstrell's avatar
sstrell
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4 years ago

It's not clear whether you're trying to create a tri-state output or a bidirectional I/O. Your ports are bidirectional, but your logic is for a tri-state output.

If it's supposed to be a tri-state, lblY1 should be an out, not inout.