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Altera_Forum's avatar
Altera_Forum
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14 years ago

vhdl querry

Dear Friends,

I have been studying a code --

write_req <= fifo_i_addr_wren and u_cmd(1);

p_data_req:process(phy_clk)

begin

if rising_edge(phy_clk) then

if reset_phy_clk = '1' then

write_req_1 <= '0';

write_req_2 <= '0';

else

write_req_1 <= write_req;

write_req_2 <= write_req_1;

end if;

end if;

end process p_data_req;

data_req <= write_req_2;

In this code the data_req is a delayed (2 clock cycles) of write_req.

I tried to understand this code - How is this delayed by 2 clock cycles? I am a conventional C coder. This is for delay of 2 cycles. If i use the same logiccc can I do for > 2 delays? How is this executed? I know that the process if-else is executed sequentially.

Can anyone explain the logic here? How is this implemented in hardware? Is it done using a mux ? How does this work out then pls?

Regards,

Vinod.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I tried to understand this code - How is this delayed by 2 clock cycles? I am a conventional C coder.

    --- Quote End ---

    A VHDL text book or tutorial would be helpful, I think.

    Generally, an assignment in a sequential edge sensitive process (e.g. using if rising_edge()) generates registers. The two cycle delay is generated by chaining two registers. If you want a longer delay, use more registers. For your convenience they can be arranged as a bit vector shifted one position on each clock.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I tried to understand this code - How is this delayed by 2 clock cycles? I am a conventional C coder. This is for delay of 2 cycles. If i use the same logiccc can I do for > 2 delays? How is this executed? I know that the process if-else is executed sequentially.

    --- Quote End ---

    Maybe your conventional C programming experience is misleading you.

    Please note the the following assignments

    write_req_1 <= write_req;

    write_req_2 <= write_req_1;

    DON'T behave as in conventional C, where you would obtain write_req = write_req_1 = write_req_2 in the end. Actually the <= assignments are performed in parallel once when the process is triggered (in your case on the clock rising edge).

    Then the second line will assign to write_req_2 the original status of write_req_1. In other words, you can change the order of the two lines without changing the result.

    This code is usually synthesized with 2 chained flip-flops, but in general the implementation of more complex code will depend on the tools you are using, like C code would result in different assembler instructions depending on compiler and optimization level.

    Regards