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Honored Contributor
Honored Contributorvhdl querry
Dear Friends, I have been studying a code -- write_req <= fifo_i_addr_wren and u_cmd(1); p_data_req:process(phy_clk) begin if rising_edge(phy_clk) then if rese...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I tried to understand this code - How is this delayed by 2 clock cycles? I am a conventional C coder. --- Quote End --- A VHDL text book or tutorial would be helpful, I think. Generally, an assignment in a sequential edge sensitive process (e.g. using if rising_edge()) generates registers. The two cycle delay is generated by chaining two registers. If you want a longer delay, use more registers. For your convenience they can be arranged as a bit vector shifted one position on each clock.
