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Altera_Forum
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14 years ago

VHDL project: is sfixed type synthesisable?

Hi, everybody! I'm going to use numbers with fixed point in my VHDL project and I need to implement it into FPGA circuit. Is the type sfixed synthesisable?
Altera_Forum's avatar
Altera_Forum
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14 years ago

i ran across a problem that made me go back to std_logic_vector for ports, but i can't remember what it was

can you use sfixed in Qsys?