Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL project: is sfixed type synthesisable?
Hi, everybody! I'm going to use numbers with fixed point in my VHDL project and I need to implement it into FPGA circuit. Is the type sfixed synthesisable?
Altera_ForumHonored Contributor
Honored Contributori ran across a problem that made me go back to std_logic_vector for ports, but i can't remember what it was
can you use sfixed in Qsys?
