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Altera_Forum
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14 years ago

VHDL project: is sfixed type synthesisable?

Hi, everybody! I'm going to use numbers with fixed point in my VHDL project and I need to implement it into FPGA circuit. Is the type sfixed synthesisable?
Altera_Forum's avatar
Altera_Forum
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14 years ago

Just as another point, if you dont do it already.

You can also use sfixed for ports (even at the top level if you want) and infer rams and multipliers from it. No need to use std_logic_vector ever.