Honored ContributorHi, everybody!
I'm going to use numbers with fixed point in my VHDL project and I need to implement it into FPGA circuit. Is the type sfixed synthesisable?
Honored ContributorQuartus doesn't support them natively yet. i have used these:
http://vhdl.org/fphdl/index.htmlHonored ContributorIve used the ones from thepancake's link for a couple of years without any problems (and they make things SOOO much easier to read when you're doing loads of fixed point).
Honored ContributorJust as another point, if you dont do it already.
You can also use sfixed for ports (even at the top level if you want) and infer rams and multipliers from it. No need to use std_logic_vector ever.Honored Contributorthepancake, thanks a lot for link!
Honored ContributorTricky, will this type be translated like integer to std_logic_vector ?
Honored Contributorsfixed is just another array of std_logic, like unsigned or signed or std_logic_vector itself.
Honored Contributorok, I've got it. Thank you!
Honored Contributori ran across a problem that made me go back to std_logic_vector for ports, but i can't remember what it was
can you use sfixed in Qsys?
