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Altera_Forum
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17 years ago

VHDL Porting from Altera to Actel

Hi Guys, I am currently designing a FPGA based camera system for a small satellite, its for my masters thesis. As my knowledge is very limited to fpga and vhdl its quite a learning curve. My Qu...
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Altera_Forum
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17 years ago

These issues can only be solved with redundant hardware. I did so providing a system to be placed into a particle beam, possibly causing damage almost everywhere in the FGPA.

I had state machines, Data RAMs and ROMS placed more than once and compared results, performed validation of the data streams and such.

The only challange was, to deter Quartus from removing the full redundant logic :-)