VHDL multiple asynchronous signal handling

Well, these are typically beginner mistakes in VHDL coding.

1. A signal/variable cannot be updated in two different Processes.
2. A signal/register/variable cannot be assigned values at both clock edges of two different clock signals.

process (signal_1, signal_2) begin
  if(signal_1) then
      signal_out <= 0;
  else
      signal_out <= 1;
  end if
end process;

In the above code, there's an issue... signal_out gets assigned 0 when signal_1 =1 and irrespective of signal_2. Same goes for the else condition. To avoid, this we have to specify all logically exclusive conditions in the if-else loop.

process (signal_1, signal_2) begin
  if(signal_1 == '1' and signal_2 = '0') then
      signal_out <= 0;
  else if (signal_1 == '0' and signal_2 == '1') then   --left out conditions are sig_1 = sig_2 == 1 , sig_1 = sig_2 == 0. 
      signal_out <= 1;  
  end if
end process;

Normally, you assign signals on the rising edge or falling edge of a periodic signal like a clock and have the other signal in the sensitivity list of the process as the reset so that the Flops in the design can be reset to a known state on Power ON.

process( clock, reset) begin
  if(reset == '0') then
      signal_out <= '0';
  else if (rising_edge/falling_edge clock) then
     signal_out <= '1'
  end if
end process

This will make sure that the code infers flip-flops and not larches or other combinational logic that is unwanted (unless or course you are designing combinational circuits, in which case you would code it in a different way.)