[VHDL] integer to std_logic or std_logic_vector conversion

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Indeed, but I need std_logic/std_logic_vector signals because it's the input signal type of my device under test...

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I was just answering your question about why integers were not binary.

Anyway - thats not a problem, we've said a conversion function isnt really that hard to do:

function int_to_sl(x : integer) return std_logic is
begin
  if x > 0 then return '1';
  else return '0';
  end if;
end function int_to_sl;
a <= int_to_sl( my_input );