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Altera_Forum
Honored Contributor
Honored Contributor[VHDL] integer to std_logic or std_logic_vector conversion
Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_ForumHonored Contributor
Honored ContributorIndeed, but I need std_logic/std_logic_vector signals because it's the input signal type of my device under test...
