[VHDL] integer to std_logic or std_logic_vector conversion

You have to remember that integers have no individual bits. Hence why they need converting to an unsigned type (which is an array of std_logic).

You can easily have a range of integer that is 0 or 1 like this:

subtype int_bool is integer range 0 to 1;

signal my_very_short_integer : int_bool;

then an assignment like this:

my_very_short_integer <= 2;

will throw an error.