[VHDL] integer to std_logic or std_logic_vector conversion

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Looks like a pretty long thread about a trivial VHDL problem.

Why don't you simply write a conversion function that returns '0'= for input = 0 otherwise '1'?

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Thanks for the "trivial VHDL problem", I'm trying to solve it for 3 days. :-P

If you look at the process, I could do it for the integer which is 0 or 1 (reset_hw_i signal), but first it's not a clean solution. I come from Verilog and if there is no way to convert it cleanly, my opinion on VHDL would be quite bad ;-)

But there are not just a "binary" integer, there is also an unsigned integer (wdogInitDelay_i on 16 bits) and I don't want to code an if statement for the 2^16 converion possibilities :-D