[VHDL] integer to std_logic or std_logic_vector conversion

I agree with FvM, a simple conversion function would make more sense to another reader.

--- Quote Start ---

 
VARIABLE wdogInitDelayVar : std_logic_vector(15 downto 0);
...
wdogInitDelayVar := to_unsigned(wdogInitDelay_i, 16)(15 downto 0);

--- Quote End ---

That wont work, because you're trying to assign an unsigned to a std_logic_vector. You need this:

wdogInitDelayVar := std_logic_vector( to_unsigned(wdogInitDelay_i, 16) );

There is no problem with this code. If Cadence keeps giving you an error about range constraints, get a better simulator.