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Altera_Forum
Honored Contributor
Honored Contributor[VHDL] integer to std_logic or std_logic_vector conversion
Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_ForumHonored Contributor
Honored ContributorLooks like a pretty long thread about a trivial VHDL problem.
Why don't you simply write a conversion function that returns '0'= for input = 0 otherwise '1'?
