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Altera_Forum
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14 years ago

[VHDL] integer to std_logic or std_logic_vector conversion

Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_Forum's avatar
Altera_Forum
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14 years ago

btw, what are you trying to compile this code in? You cannot compile this code in Quartus, which is probably why you're getting a range constraint violation, because Quartus wants to map integers to 32 bits, and you only asked for 1 bit. (As well as non of the textio stuff being appropriate).

The first line should work fine in Modelsim.