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Altera_Forum
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14 years ago

[VHDL] integer to std_logic or std_logic_vector conversion

Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_Forum's avatar
Altera_Forum
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14 years ago

using the temporary variable should work fine. Is it because you forgot a space between downto and 0?

And in your origional post, there are no wait until statements in your code. But note that you cannot have a sensitivity list and wait statements, its one or the other.