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Altera_Forum
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14 years ago

[VHDL] integer to std_logic or std_logic_vector conversion

Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you for your answer...

First, the device under test needs std_logic signals as input signals, then, I'll need to convert unsigned to std_logic_vector.

I tried your trick reset_hwVar := to_unsigned(reset_hw_i, 1)(0); but it doesn't work.

If you've any other idea, don't hesitate...