Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

[VHDL] integer to std_logic or std_logic_vector conversion

Hello, I've some issues to convert integer to std_logic or std_logic_vector. I need to do so for a testbench which reads stimuli (binary or positive integers) in a text file, stores it as intege...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

First, you could try to work only with unsigned signals and to ban all std_logic_vector. I don't know if it's the very good idea but it works great for me.

Then to create an std_logic signal, something like this should work :

reset_hwVar := to_unsigned(reset_hw_i, 1)(0);