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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL: How to add a Description to the Symbol Properties box of the generated symbol?

Hi,

When generating a symbol using a generic like below: 

entity Attenuation is
    generic (
        PIXEL_CNT_WIDTH      : integer := 11;-- default value
        LINE_CNT_WIDTH       : integer := 10 -- default value
    );
    port (
        clock : in std_logic;
        resetn : in std_logic;

We can set the generic values using the Symbol Properties dialog box. In this box we have access to a Description field for each generic parameter. Does anybody know how to enter some text in these fields directly from the VHDL used to generate the symbol?

Thanks in advance for your help.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Without passing the vhdl file through a prepocessor (a script of some sort) before vhdl compile I don't think it's possible.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Maybe the best thing to do is not to use the graphic editor and instatiate your entities in VHDL instead - then you can have as much description as you want.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi,

    --- Quote Start ---

    Maybe the best thing to do is not to use the graphic editor and instatiate your entities in VHDL instead

    --- Quote End ---

    However my design habits are to always design a graphical top. Then I design in VHDL at all levels below. This is why my question is related to the graphic symbols and their options.

    Anybody else?