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Altera_Forum's avatar
Altera_Forum
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14 years ago

[VHDL] Different synthesis results after using "generate"

Hello, I used 'generate' statement to order several similar components, but after that synthesis results are slightly different. Does anyone know what can cause this? Theoretically there is no d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok, thanks. Resource utilisation is a little different too, but I'll send it for testing anyway.