[VHDL] Different synthesis results after using "generate"

Thanks for replies. By "results" I mean resource utilisation and timing analysis results.

I have a FIR filter with a chain of 8 MAC modules:

--- Quote Start ---

mac0 : mac

port map ( aclr0 => mac_rst,

clock0 => clk,

dataa => sample(0),

datab => coeff(0),

overflow => of(0),

result => sum(0)

);.

.

.

mac7 : mac

port map ( aclr0 => mac_rst,

clock0 => clk,

dataa => sample(7),

datab => coeff(7),

overflow => of(7),

result => sum(7)

);

--- Quote End ---

Sample, coeff and sum are arrays of vectors.

Instead, I wrote it like this:

--- Quote Start ---

mac_components : for i in 0 to 7 generate

begin macs : component mac

port map(mac_rst, clk, sample(i), coeff(i), of(i), sum(i));

[/INDENT]end generate mac_components;

--- Quote End ---

I'm not sure about this change because, according to TQ, timing results are a bit worse (but still within margin).

Should I be so careful with this type of code?