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Altera_Forum's avatar
Altera_Forum
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14 years ago

[VHDL] Different synthesis results after using "generate"

Hello, I used 'generate' statement to order several similar components, but after that synthesis results are slightly different. Does anyone know what can cause this? Theoretically there is no d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Assuming by "results" you mean testing results then either you observation is wrong or your test is wrong or your connections are wrong or you have timing violations.

Without further information, it is only matter of speculations

If by "results" you mean resource utilisation then a difference is not a surprise.