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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL description a register

Hi there,

I just started learning VHDL, and I have learn how to write a description for combinational and sequential circuit. and I got this question in my book and i'm absolutely lost with it, where the question is asking me to write a description in VHDL for below system.

please help!

Design a system with an 8-bit input I that can be stored in 8-bit registers A, B, and/orC when input La, Lb, and/or Lc is 1, respectively. So if inputs La and Lb are 1, then registers A and B will be loaded with input I, but register C will keep its current value. Furthermore, if input R is 1, then the register values swap such that A=B, B=C, and C=A. Input R has priority over the L inputs. The system also has one clock input. Describe this circuit using VHDL.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Hi there,

    I just started learning VHDL, and I have learn how to write a description for combinational and sequential circuit. and I got this question in my book and i'm absolutely lost with it, where the question is asking me to write a description in VHDL for below system.

    please help!

    Design a system with an 8-bit input I that can be stored in 8-bit registers A, B, and/orC when input La, Lb, and/or Lc is 1, respectively. So if inputs La and Lb are 1, then registers A and B will be loaded with input I, but register C will keep its current value. Furthermore, if input R is 1, then the register values swap such that A=B, B=C, and C=A. Input R has priority over the L inputs. The system also has one clock input. Describe this circuit using VHDL.

    --- Quote End ---

    Since this is homework, I won't give the full answer but enough to get you started: 

     
entity Homework(
   Clock:  in  std_ulogic;
   -- List your other inputs and outputs here also:  La, Lb, Lc, I
   -- Make the outputs of type 'buffer' like this
   A:  out std_ulogic_vector(7 downto 0)
);
end Homework; -- don't you wish?
 
architecture rtl of Homework is
begin
   process(Clock)
   begin
      if rising_edge(Clock) then
         -- Now use some if/then statements to implement what you've
         -- described in words.  You'll be assigning to the outputs A, B, C
         -- something like this
         if (La = '1') then
            A <= I;
         -- More stuff...
      end if;
end rtl;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi K_J,

    Thx for yr reply. Based on yr help, i can work out something. But, there is one point about "keeping current value of C", that I dont know how to write down, could you please help me abit further. 

    
if(R = '1') then 
        A<=B;
        B<=C;
        C<=A;
else
        if(La='1') then 
         A<=I
        else if(Lb='1') then 
         B<=I
   else   
      --what shoul i write here, to describe that C will keep its current value?
      --could i write:   C <= C;   ?
    end if;
end if;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Thx for yr reply. Based on yr help, i can work out something. But, there is one point about "keeping current value of C", that I dont know how to write down, could you please help me abit further.

    --- Quote End ---

    There's no need of a C<=C statement

    Registers, such A,B and C are, will preserve the actual state until you reassign them. So you only need to specify the load condition, when any of the Lx input is active.

    A remark to your current code:

    The system description states : "So if inputs La and Lb are 1, then registers A and B will be loaded with input I, but register C will keep its current value".

    This means that when two (or more) Lx inputs are active, you are supposed to load both the registers with I. Then you should not use a if... else structure but rather: if La ... if Lb ... if Lc...