Altera_Forum
Honored Contributor
15 years agoVHDL_Debugging help
I'm trying to write some VHDL code for a 3 to 8 decoder, but I get the same error all the time what is wrong with my code, I have also attached a screen shot of the program and errors.
library IEEE; use IEEE.std_logic_1164.all; ENTITY 3to8decoder IS PORT ( A,B,C :IN std_logic; Y :OUT std_logic_vector (7 DOWNTO 0)); END 3to8decoder; ARCHITECTURE decoder_C OF 3to8decoder IS signal ABC: std_logic_vector(2 DOWNTO 0); BEGIN ABC <= A & B & C; WITH ABC select Y <= “00000001” WHEN “000”, “00000010” WHEN “001”, “00000100” WHEN “010”, “00001000” WHEN “011”, “00010000” WHEN “100”, “00100000” WHEN “101”, “01000000” WHEN “110”, “10000000” WHEN other;-----> the error is here it says there is a syntax error. END decoder_C; Thank you Heath