VHDL_Debugging help

I'm still getting errors I changed all the double " to single, and got less errors, stille getting 4 thow.

library IEEE;

use IEEE.std_logic_1164.all;

ENTITY decoder3to8 IS

PORT (

A,B,C :IN std_logic;

Y :OUT std_logic_vector (7 DOWNTO 0));

END decoder3to8;

ARCHITECTURE decoder_C OF decoder3to8 IS

signal ABC: std_logic_vector(2 DOWNTO 0);

BEGIN

ABC <= A & B & C;

WITH ABC select

Y <= '00000001' WHEN '000', --here is the error and line:Error (10500): VHDL syntax error at 3to8decoder.vhd(14) near text "'"; expecting "(", or an identifier, or unary operator

'00000010' WHEN '001',

'00000100' WHEN '010',

'00001000' WHEN '011',

'00010000' WHEN '100',

'00100000' WHEN '101',

'01000000' WHEN '110',

'10000000' WHEN others;

END decoder_C;