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Altera_Forum's avatar
Altera_Forum
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14 years ago

VHDL comparison

Hi all, I'd like to write a limiter: 1. Input/output are 16 bit signed number 2. If input is -32768 then output is limited by -32767, otherwise the output is just bypass of the input....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Try this: 


process(clk)
  begin
    if rising_edge(clk) then
      if (data_in = X"8000") then
        data_out <= X"8001";
      else
        data_out <= data_in;
      end if;
  end if;
end process;
Cheers,

Dave