Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

VHDL Code Of 2 input XOR -gate

Hi,

I am new to VHDL programing and i had written a VHDL code on 2 input XOR gate using process and it compiles successfully but in test bench waveform i am unable to get the output that is for all possible inputs i am getting 0 output , I am using Xilinx 9.1 and the following is code

entity XOR2 is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : out STD_LOGIC);

end XOR2;

architecture Behavioral of XOR2 is

begin

process(A,B)

begin

if((A='0') and (B='1')) then

C<='1';

elsif((A='1') and (B='0')) then

C<='1';

else

C<='0';

end if;

end process;

end Behavioral;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You can just use the inbuilt function xor(without process)

    C <= A xor B;

    I wonder if your entity name xor2 is legal since I think there is an inbuilt vhdl function in that name.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    hi

    Thanks for information but i want to implement it with process so is it possible
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Your process looks ok to me

    though you can simplify it to: 

    
process(A,B)
begin
if (A = '1' and B = '0') or (A = '0' and B = '1') then
     C <= '1';
else
     C <= '0';
end if;
end process;

    either way it should work. Change the entity name to something other than xor2 just in case. Otherwise there is some thing wrong with your observation.