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Altera_Forum
Honored Contributor
Honored ContributorVHDL code for PC-FPGA connection
Hi to everyone,
I want to connect my PC with the FPGA with a fast connection using low-level codes. That is, I don't want to use NIOS processor since I have my own data-mining oriented blocks and I need all the FPGA Logic Elements as possible for this task. The problem is that I have to transfer Gigabytes of information from the PC to the FPGA in reasonable times. I though to use an ethernet connection for this or maybe an USB connection but I need low-level codes for this task. How can I get these codes (in VHDL format as an example)?. In fact probably this is a common problem for FPGA users. Can anyone help me with this? Thank you! Josep Lluís from Spain.1 Reply
Altera_ForumThis still has Nios II in it but it's there to do control type stuff and not in the actual data path: http://www.alterawiki.com/wiki/nios_ii_udp_offload_example
If I remember correctly that design exposes 1-4 TX and 1-4 RX ports that can swamp a 1Gbps link.
