Vhdl code for IP_IRQ component!

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Hi, I need help for Vhdl code for designing one IP component, small device drivers and test demonstration that give a periodic interrupt to sierra every second.

"SEE ATTACHMENT"

Component level interface (VHDL) is:

PORT (

addr : IN std_logic_vector(1 downto 0);

clk : IN std_logic;

cs_n : IN std_logic;

read_n : IN std_logic;

din : IN std_logic_vector(31 DOWNTO 0);

reset_n : IN std_logic;

write_n : IN std_logic;

dout : OUT std_logic_vector(31 DOWNTO 0);

irq_out_n : out std_logic_vector(1 downto 0) ) ;

END;

I attached also a vhdl code(IP_IRQ) that i wrote but is not working. I don’t know what’s wrong.

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Hi,

can you describe your problem a little bit more ? I could see at least one problem.

irq_out_n(1) is only set in the reset branch. I would assume that Quartus would

generate a latch for irq_out_n(1).

Kind regards

GPK

a couple of things:

dont use std_logic_unsigned/signed/arith at the same time as ieee.numeric_std. I recommend using numeric_std.

you cant compare a std_logic vector to a integer literal, you have to compare it to a string. For a hex string you need to write x"5e7". A std_logic_vector is NOT an integer, its a collection of bits.