vhdl code error

hi i am getting an error of Can't infer register for "bbpa[0]" at spim2.vhd(127) because it does not hold its value outside the clock edge while compiling the following code entity spim2 is Port ( --Master_Clk : in STD_LOGIC; -- Load : in STD_LOGIC; --Datain: in STD_LOGIC_VECTOR( 15 DOWNTO 0); bbpa : buffer std_logic_vector ( 11 downto 0); bbpd : inout std_logic_vector (15 downto 0); spi_cntrl_clk : buffer STD_LOGIC;--spi master clock spi_cntrl_sync:buffer std_logic;--wirte sync spi_cntrl_data : out STD_LOGIC; multidrop_uc2 : in STD_LOGIC;--read data MULTIDROP_UC1 : in STD_LOGIC; proclk66m: buffer std_logic;--processor bus clock bbpwe: in std_logic_vector(1 downto 0);---processor write enable when both the bits are set low --by processor ,it writes data into the data bus -- -- master spi signals tdata: buffer std_logic_vector (15 downto 0); twriteaddress:buffer std_logic_vector (11 downto 0); trdaddress : buffer std_logic_vector(11 downto 0); treadclock : buffer std_logic; --twriteclock : buffer std_logic; trd_en : buffer std_logic; twr_en : buffer std_logic; tout : buffer std_logic_vector(15 downto 0); --slave spi signals rin : buffer std_logic_vector(15 downto 0); rwriteaddress:buffer std_logic_vector (11 downto 0); rrdaddress : buffer std_logic_vector (11 downto 0); rreadclock : buffer std_logic; rwriteclock : buffer std_logic; rrd_en : buffer std_logic; rwr_en : buffer std_logic ); -- write sync Slave Chip Select#1 end spim2; architecture Behavioral of spim2 is -- signal tShreg: STD_LOGIC_VECTOR( 15 DOWNTO 0) := "0000000000000000"; -- signal rShreg: STD_LOGIC_VECTOR( 15 DOWNTO 0) := "0000000000000000"; -- -- type States is (Idle,Data_transfer,Stop); -- signal State: States := Idle; -- shared variable Count1: integer range 0 to 15; -- component tbuffer PORT ( data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); rdclock : IN STD_LOGIC ; rden : IN STD_LOGIC := '1'; wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); wrclock : IN STD_LOGIC ; wren : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); end component; component rbuffer PORT ( data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); rdclock : IN STD_LOGIC ; rden : IN STD_LOGIC := '1'; wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0); wrclock : IN STD_LOGIC ; wren : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); end component; begin tbuffer_inst : tbuffer PORT MAP ( data =>tdata , rdaddress => trdaddress, rdclock =>treadclock, rden => trd_en , wraddress => bbpa,--twriteaddress wrclock => proclk66m , wren => twr_en, q => tout ); rbuffer_inst : rbuffer PORT MAP ( data => rin, rdaddress => rrdaddress , rdclock => rreadclock, rden => rrd_en, wraddress => rwriteaddress, wrclock =>rwriteclock, wren => rwr_en , q => bbpd ); process(proclk66m , bbpwe) --variable c1: integer range 0 to 75 :=0; --variable c2: integer; --range 0 to 75 :=0; begin if(bbpwe="00") then bbpa