VHDL code_1

Hello guys

I have one more problem with the altera Vhdl code using max_plus_II

I wirte this simple code :

ibrary ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity PWM_n4 is

port

(

clk48Mhz : in std_logic;

encoder : in std_logic_vector(13 downto 1);

cntr_in : in std_logic_vector(12 downto 0);

out_signal : out std_logic

);

end;

architecture arc_PWM_n4 of PWM_n4 is

signal signal_out : std_logic := '0';

signal cntr : integer range 0 to 4861 := 0;

signal reset_cntr : std_logic := '0';

signal n_encoder : std_logic_vector(13 downto 1) := encoder;

signal reset_encoder : std_logic := '1';

begin

process

begin

if rising_edge(clk48Mhz) then

if reset_cntr = '1' then

cntr <= 0;

else

cntr <= cntr + 1;

end if;

if reset_encoder = '1' then

n_encoder <= encoder;

end if;

end if;

end process;

process(clk48Mhz)

begin

if falling_edge(clk48Mhz) then

reset_cntr <= '0';

reset_encoder <= '0';

if cntr = cntr_in then

if signal_out = '1' then

signal_out <= '0';

else

signal_out <= '1';

end if;

else if cntr = 4860 then

signal_out <= '1';

else if cntr = 4861 then

reset_cntr <= '1';

reset_encoder <= '1';

end if;

end if;

end if;

end if;

end process;

out_signal <= signal_out;

end;

when I simulate this code I got the results I need, but when I connect this code to a output pin and the pin to a scope, the scope shows me the opposite of what the simulator shows.

what should I do, why it is behave like that? it should be the same not the opposite.

thx a lot