Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL code_1
Hello guys I have one more problem with the altera Vhdl code using max_plus_II I wirte this simple code : ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use i...
Altera_ForumHonored Contributor
Honored ContributorI would try adding asynchronous reset signal. It would look something like this:
begin process begin if asynchronous_reset = '1' then --here you can put init values to signals, for example: out_signal <= (others => '0'); elsif rising_edge(clk48Mhz) then if reset_cntr = '1' then cntr <= 0; else cntr <= cntr + 1; end if; if reset_encoder = '1' then n_encoder <= encoder; end if; end if; end process; I assume that your output is logically inverted. You can also add simple output inverter. It will solve your problem easily :)
