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Altera_Forum
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18 years ago

VHDL code_1

Hello guys I have one more problem with the altera Vhdl code using max_plus_II I wirte this simple code : ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use i...
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Altera_Forum
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18 years ago

Hi

Which one is correct?? I mean the simulated stuff or the actual signal on the pin.

check up your simalution and synthesis settings....

my guess is in either of this you are enabling inverted output generation..