[vhdl] artificial neural network

But I use modelsim directly and the compile menu is bleak so inactive. Despite the simulation is. In the quatrus this two options is not active. But my Modelsim is just of starter edition. So it was said that it just performs the simulation despite it also do compilation. And in the whole: is it only way to compose logic circuit in altera through the vhdl(verilog) code or are there some graphical editor that would do the same job, as well as create the code based on graphics.