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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL advice needed - multiplicating combinational logic.

I have a piece of code that I want implemented as combinational logic, but I want 16 identical modules of it.

Currently I'm doing something like 

       
for i in 0 to OUTPUTNO-1 loop
   outputs(i) <= outputsignal(i) and not outputban(i);
end loop;

But afaik, that kind of loop is only allowed inside a process, which I have to declare as sensitive to outputsignal and outputban (which are of type array of std_logic).

Is there any more generic way of duplicating code in VHDL, that works outside of a process also?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Is there any more generic way of duplicating code in VHDL, that works outside of a process also?

    --- Quote End ---

    Yes, its called a generation loop. Your code just needed a label and a slight change in syntax: 

           
g1: for i in 0 to OUTPUTNO-1 generate
   outputs(i) <= outputsignal(i) and not outputban(i);
end generate;

    Cheers,

    Dave