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Altera_Forum
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14 years ago

VHDL advice needed - multiplicating combinational logic.

I have a piece of code that I want implemented as combinational logic, but I want 16 identical modules of it. Currently I'm doing something like for i in 0 to OUTPUTNO-1 loop output...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Is there any more generic way of duplicating code in VHDL, that works outside of a process also?

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Yes, its called a generation loop. Your code just needed a label and a slight change in syntax: 

       
g1: for i in 0 to OUTPUTNO-1 generate
   outputs(i) <= outputsignal(i) and not outputban(i);
end generate;

Cheers,

Dave