Altera_Forum
Honored Contributor
Honored Contributorvhdl -division program
hi to all
if anybody having coding for division please do help meForum Discussion
31 Replies
Altera_Forum--- Quote Start --- if you want to do division of any significant bitwidth (>3~4 bits num and den), you need to instantiate the divider megafunction --- Quote End --- Cyclone III achieves > 50 MHz for a 8:8 Bit signed and > 40 MHz for a 12:8 Bit unsigned divider (between registers). This is at least a significant bitwidth at reasonable clock frequency, I think. If you want more, you need divider internal pipelining and the alt_div MegaFunction.- Altera_Forum
you can try adding some extra registers and turning on register retiming, but lpm_divide seems to have significantly better performance.
- Altera_Forum--- Quote Start --- you can try adding some extra registers and turning on register retiming --- Quote End --- Sounds like poor mans pipelining, but an interesting suggestion though. Seriously, if the infered divider doesn't achieve the intended speed, you should use an explicite instantiation.
- Altera_Forum--- Quote Start --- It does, under the conditions I told. (Valid at least for V9.0 and later). --- Quote End --- If i use version 9 or later will it accept the division . i have not yet used version 9.
- Altera_Forum
Divider interference works with previous Quartus versions as well, I checked V6.0 and V8.1. I guess, you ignored the other points that have been said in the above discussion.
- Altera_Forum
Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead.
a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can. - Altera_Forum--- Quote Start --- Or the best solution is to redesign the algorithm so that you dont have to do the divide in the first place - stick to multiplies instead. a/b = a * 1/b. Do the 1/b function on something else (like a processor) if you can. --- Quote End --- but 1/b also has a division then how can it accept?. or how to do it
- Altera_Forum--- Quote Start --- but 1/b also has a division then how can it accept?. or how to do it --- Quote End --- Hence why I said take it off FPGA onto something like a processor. Division can be done fine on an FPGA, it just eats through resources.
- Altera_Forum
If speed is not important you could fall back on a serial divider mechanism, doing 'long division' in binary.
- Altera_Forum--- Quote Start --- Sounds like poor mans pipelining, but an interesting suggestion though. --- Quote End --- if by poor you mean lazy, certainly. :) it would be nice if register retiming could meet the fmax of an lpm function. i haven't found it to do so with wide multipliers (24 bit) in CIII either.
