vhdl -division program

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if you want to do division of any significant bitwidth (>3~4 bits num and den), you need to instantiate the divider megafunction

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Cyclone III achieves > 50 MHz for a 8:8 Bit signed and > 40 MHz for a 12:8 Bit unsigned divider (between registers). This is at least a significant bitwidth at reasonable clock frequency, I think. If you want more, you need divider internal pipelining and the alt_div MegaFunction.