VHDL - bit set, or net set?!?

Maik,

I can't give you a definitive answer as I don't fully understand your code, but what I can see is that you have multiple nested if-statements in a huge process block, with interchanged levels for fb_pt_read_byte_counter and processing_state_register.

Here are some tips:

1. Break down the code into multiple smaller process blocks.

2. Use a FSM.

3. Remove as much as possible nested if-statement.

Keep in mind that VHDL is a language to describe parallel hardware.

Try not to think of it as sequential code.