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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

VGA Timing problem

Hi guys, I'm on an Altera DE1 board and I've just gotten my hands dirty with trying to output to a VGA monitor, and its not going as well as I'd like. I've been using

*well apparently I can't post urls... if you google "vga timing lasierra" its the first result, a pdf file*

to try and get the idea of it and I've struggled with that, but I've been trying to recreate their circuit and then mess around and try to understand it more. For a while, when I misunderstood the idea a bit (I kept the hsync cycles running repeatedly, not just in the specified window of the vsync cycle), I got the monitor to show "black" and not go into power saving mode. I even got it to show very brief flashes of color when I made the RGB values match KEY/SW values on the board, but since I realized I'd been doing it wrong I haven't even gotten that. Seems odd that when I rework things to make them "right", I go back in progress...but oh well. As far as I can tell, I'm following their circuit (Figure 5, a-d) closely, but no luck. As you can see, I'm using a 50MHz clock and turning into a 25 MHz clock, while the site says use 25.175MHz..could that be the problem? Also if there are other problems with the code I'd welcome suggestions, but the timing issue is my main priority here. Thanks! 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vgatest is
PORT (	C50 : in BIT;
		SW : in UNSIGNED(9 downto 0);
		KEY : in UNSIGNED(3 downto 0);
		LEDG : out UNSIGNED(7 downto 0);
		VGA_R,VGA_G,VGA_B : out UNSIGNED(3 downto 0) := "0000";
		VGA_HS : out BIT := '1';
		VGA_VS : out BIT := '1';
		DEB1 : out INTEGER;
		DEB2 : out INTEGER
		);
end vgatest;
architecture vtbehav of vgatest is
signal C25 : bit := '0';
signal H_READY : boolean := true;
signal V_READY : boolean := true;
signal H_CNT : integer := 0;
signal V_CNT : integer := 0;
signal RDATA, GDATA, BDATA: UNSIGNED(3 downto 0) := "1111";
begin
	process(C50)
		begin
		if C50'event and C50 = '1' then
			C25 <= not(C25);
		end if;
	end process;
	process(C25)
		begin
		if C25'event and C25 = '1' then
			if H_READY and V_READY then
				VGA_R <= "0000";
				VGA_G <= "0000";
				VGA_B <= "1111";
			end if;
			
			H_CNT <= H_CNT + 1;
			
			
		--HSYNC
			if H_CNT = 640 then 
				H_READY <= false;
			elsif H_CNT = 660 then 
				VGA_HS <= '0';
			elsif H_CNT = 755 then 
				VGA_HS <= '1';
			elsif H_CNT = 800 then 
				H_READY <= true;
				H_CNT <= 0;
				V_CNT <= V_CNT + 1;
			end if;
		end if;
	end process;
			
	process(C25)
		begin
		if C25'event and C25 = '1' then
			--VSYNC
			if V_CNT = 480 then 
				V_READY <= false;
			elsif V_CNT = 494 then 
				VGA_VS <= '0';
			elsif V_CNT = 496 then
				VGA_VS <= '1';
			elsif V_CNT = 528 then 
				V_READY <= true;
			end if;
		end if;
	end process;
	
DEB1 <= H_CNT;
DEB2 <= V_CNT;
end vtbehav;

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    you might want to look at using a pll to generate the right clock speed

    you have a 27MHz clock on the DE1 board which you can use to drive the Pll

    pll's can be generated by megawizards

    does that mean anything?

    look for PLL and mega wizard

    post back how you get on, and i'll help you a bit more if you can ask the right questions!

    (I have already done all this, I just want to make sure you look for yourself

    Thats what this forum has always done for me, and it works and I always learn more that way)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I didn't know that existed, I'm checking it out right now. So far, if I've set it up right, it hasn't helped, still on the "ON" black screen :/ I'm doing a big simulation right now to try and make sure I did it right.

    Here is my updated code: 

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vgatest is
PORT (	C24 : in BIT;
		SW : in UNSIGNED(9 downto 0);
		KEY : in UNSIGNED(3 downto 0);
		LEDG : out UNSIGNED(7 downto 0);
		VGA_R,VGA_G,VGA_B : out UNSIGNED(3 downto 0) := "0000";
		VGA_HS : out BIT := '1';
		VGA_VS : out BIT := '1';
		DEB1 : out INTEGER;
		DEB2 : out INTEGER;
		DEB3 : out boolean;
		DEB4 : out boolean
		);
end vgatest;
architecture vtbehav of vgatest is
signal C252 : bit := '0';
signal H_READY : boolean := true;
signal V_READY : boolean := false;
signal H_CNT : integer := 0;
signal V_CNT : integer := 494;
signal RDATA, GDATA, BDATA: UNSIGNED(3 downto 0) := "1111";
component vgapll is
PORT(	inclk0		: IN BIT;
		c0		: OUT BIT ;
		locked		: OUT BIT 
	);
end component;
begin
	VGACLK : vgapll port map(C24, C252);
	
	process(C252)
		begin
		if C252'event and C252 = '1' then
			H_CNT <= H_CNT + 1;
		--HSYNC
			if H_CNT = 640 then 
				H_READY <= false;
			elsif H_CNT = 660 then 
				VGA_HS <= '0';
			elsif H_CNT = 755 then 
				VGA_HS <= '1';
			elsif H_CNT = 800 then 
				H_READY <= true;
				H_CNT <= 0;
				V_CNT <= V_CNT + 1;
			end if;
	
			--VSYNC
			if V_CNT = 480 then 
				V_READY <= false;
			elsif V_CNT = 494 then 
				VGA_VS <= '0';
			elsif V_CNT = 496 then
				VGA_VS <= '1';
			elsif V_CNT = 528 then 
				V_READY <= true;
				V_CNT <= 0;
			end if;
			
			if H_READY and V_READY then
				VGA_R <= "0000";
				VGA_G <= "0000";
				VGA_B <= "1111";
			end if;
		end if;
	end process;
	
DEB1 <= H_CNT;
DEB2 <= V_CNT;
DEB3 <= H_READY;
DEB4 <= V_READY;
end vtbehav;

    EDIT: The PLL didn't solve my problem, but the timing seems to be better, but made the simulation take waaaaay too long. I'll try it with any new solutions to see if maybe it needs a more precise clock AND whatever the solution is here. BTW the closest I could get the new clock to was 25.20 MHz, with the intended clock 25.175MHZ.

    EDIT 2: HA! I never turned the VGA_R/G/B OFF on the front/back porch! :D It works now.