VGA 25MHz, Clock 100MHz, Help!

Here is a vga example with a reduced pixel clock (should run at 100MHz for 25MHz Pixelclock)

If you need other resolution, just modify some counters and fixed values.

//***************************************************************************************************************************************************

// definitions, includes

//======================

// synthesis translate_off

`timescale 1ns / 1ps

// synthesis translate_on

module video_vga_lcd_640x480 (

gls_clk,

reset_n,

nHSync,

nVSync,

HBlank,

VBlank,

Red,

Green,

Blue,

ActiveArea,

XPixel,

YPixel

);

input gls_clk;

input reset_n;

output nHSync;

output nVSync;

output HBlank;

output VBlank;

output Red;

output Green;

output Blue;

output ActiveArea;

output [ 9: 0] XPixel;

output [ 9: 0] YPixel;

reg [1:0] slowdown4to1;

always @ (posedge gls_clk)

slowdown4to1 <= slowdown4to1 + 2'd1;

wire EnablePixelClk;

assign EnablePixelClk = !slowdown4to1;

// Horizontal

// 640 Pixel

// 48 Front Porch

// 96 Sync

// 16 Back Porch

// 800 Pixel pro Zeile

reg [ 9: 0] XPixel;

always @ (posedge gls_clk)

if ( XPixel === 10'd799 )

XPixel <= 10'd0;

else

XPixel <= ( EnablePixelClk ) ? XPixel + 10'd1 : XPixel;

reg HBlank;

always @ ( posedge gls_clk )

if ( XPixel === 10'd639 ) // Start of Front Porch

HBlank <= 1'b1;

else if ( XPixel === 10'd799 ) // End of Back Porch

HBlank <= 1'b0;

else

HBlank <= HBlank;

reg nHSync; // 640 -1 + 16 till 640 - 1 + 96

always @ ( posedge gls_clk )

if ( XPixel === 10'd655 ) // Start of HSync

nHSync <= 1'b0;

else if ( XPixel === 10'd735 ) // End of HSync

nHSync <= 1'b1;

else

nHSync <= nHSync;

// Vertikal

// 480 Videolines

// 10 Front Porch

// 2 Sync

// 33 Back Porch

// 525 Lines total

reg [ 9: 0] YPixel;

always @ ( posedge gls_clk )

if ( XPixel === 10'd799 )

if ( YPixel === 10'd524 )

YPixel <=10'd0;

else

YPixel <= YPixel + 10'd1;

else

YPixel <= YPixel;

reg VBlank;

always @ ( posedge gls_clk )

if ( XPixel === 10'd799 )

if ( YPixel === 10'd479 ) // Start of Front Porch

VBlank <= 1'b1;

else if ( YPixel === 10'd524 ) // End of Back Porch

VBlank <= 1'b0;

else

VBlank <= VBlank;

else

VBlank <= VBlank;

reg nVSync; // 480 - 1 + 10 till 480 - 1 + 10 + 2

always @ ( posedge gls_clk )

if ( XPixel === 10'd799 )

if ( YPixel === 10'd489 ) // Start of VSync

nVSync <= 1'b0;

else if ( YPixel === 10'd491 ) // End of VSync

nVSync <= 1'b1;

else

nVSync <= nVSync;

else

nVSync <= nVSync;

wire ActiveArea;

assign ActiveArea = !HBlank && !VBlank;

wire Red;

assign Red = ActiveArea && XPixel[2];

wire Green;

assign Green = ActiveArea && XPixel[5];

wire Blue;

assign Blue = ActiveArea && XPixel[8];

endmodule