Forum Discussion
Altera_Forum
Honored Contributor
16 years agoeject is right, I should be using 25.175 MHz, not 25 MHz. This is now corrected.
I am now using CLOCK_27 to generate the 25.175MHz clock, and CLOCK_50 to generate the 100MHz clock. I have included a small test verilog module called vgatest in the vgatest.v attachment. It shows exactly what I am trying to achieve: Generating a counter at the normal clock, and feeding this to vga output. However, when I program this test, my vga screen output is shaking. When I move all the counter logic into the vga_clk domain, the image is correct and clean. This is ofcourse not an option, since the color needs to be generated from the normal clock. MSchmitt, can you explain in more detail the DFF method? I don't quite understand what you mean. Regards