Forum Discussion
Occasional Contributorvery noisy outputs on EPM3064
Occasional ContributorMeanwhile I tested various changes, but the spikes on the outputs are still there. I added 100 uF between the power pins but no influence on 1 kHz spikes.
Now I can provide some more images.
- clock1kHz.png: CLK input from test output of my oscilloscope, amplitude reduced by serial resistor and parallel zener diode
- clock1kHz_zoomed.png: positive edge of CLK input zoomed
- VCC-AC.png: VCC with AC coupling to oscilloscope, CLK input connected
- VCC-AC-noOsci.png: same as above but Oscilloscope disconnected (only ground is connected). As can be seen, some 1kHz noise is picked up in my test configuration.
When CLK input is disconnected all spikes on VCC are gone.
With every positive edge of CLK the chip seems to sink a lot of current which cannot be provided by the capacitors. Generally this means that every synchronous design will suffer from this effect. The more macrocells a design uses the more severe these effects will be.
On my fully equiped testboard there is a 7 segment display with common cathode, i.e. the outputs of EPM3064A have to provide current to the LEDs in the display. This might increase the problem with spikes.
Is EPM3064A suitable for a synchronous design?
Are there chips which are better with respect to current spikes?
Frequent ContributorThe EPM3K/7K series are absolutely suitable for synchronous design. I have used them in that way for years with clock rates from 10MHz up to 50MHz.
The noise spikes on the clock edges are not unexpected, as current will be drawn during signal transitions. Unfortunately the spikes will be exaggerated in your design because of the poor quality of your power distribution. Your traces on the two layer board will be highly inductive and are causing this noise to be generated on the power rails. Depending on your LED series resistor values you might also see high current draw (which in an inductive environment causes ringing) from the LED currents.
For reference, my test board designs for the EPM7064S and EPM3064A series PLCC44 parts use a four layer design with full power and ground planes under the device. Local 10uF bulk decoupling. No individual 100nF devices. Using a 50MHz CMOS oscillator and a design which has 60 registers and 64 macrocells as three simultaneous 18b binary counters I see no more than 100mV of noise on the power rail (5V or 3.3V as applicable to the device).
Also, on your BCD to seven segment decoder outputs, they are not synchronous, it is just logic, so expect to see switching noise on the edges as the 4b synchronous counter values propagates thru the logic. They may bounce up and down for 10 to 20ns after each clock edge. That is expected for non registered outputs.
PS: one additional thought ... what type of probing arrangement did you use on your scope to capture the waveforms?
I am guessing it is a probably 10X scope probe and there is a ground lead of 10cm or so in length that you connected to a ground point.
If so, this can add additional ringing on the measured signal due to the probing ground loop (it is inductive) that is not really there.
Ideally you would use a probe with an adjacent 2.5mm or so ground connection clip so there is no long ground loop connection.
Just thought I would ask ...
- Niko3
Thank you telling me about your experience and examples.
What is your opinion about the chances to achieve good results with a 2 layer design and wider power rails?
Do you know or hear about successful 2 layer designs with EPM3064A?
If not all pins of the chip are used, VCC power rails can be made wider. And a ground plane like in my layout always is possible.
- _AK6DN_
I have done two layer designs using the EPM7032S and EPM7064S parts in the PLCC44 package in thru hole sockets.
They worked fine. The boards were all done with thru hole parts so it was easy enough to provide power using 25 to 50 mil traces.I have not done two layer boards using the TQFP44 packages; those have all been four layer designs with a power/ground plane.
Most all the other components were surface mount as well, and the layout packed pretty tight. The added cost (basically a 4 layer board is 2X the cost of a 2 layer board) for a small prototype board in the 50mm x 100mm range was acceptable.Using power and ground islands under the TQFP package, and multiple small vias for connecting the power pins to the islands should be achievable. But you need to implement the power/ground solution first, and then squeeze in the signal traces after.
