Forum Discussion
New ContributorVery high interconnect delay
The design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays.
Why huge clock skew you might ask? That's because this is a cross-clock transfer.
Occasional ContributorThe design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays.
Why huge clock skew you might ask? That's because this is a cross-clock transfer.
New ContributorHello skyjuice,
Thanks for putting me on the right tracks. Although I don't know about cross-clock transfer (could you possibly point me to some literature?). What I understand from your response is clock skew is so high, partially, due to use of DDIO buffer (which introduce additional delay to the required path). Removing it and modifying output delays to be referenced to FPGA pin solved the problem.
Modified constraints:
