New ContributorVery high interconnect delay
Hello,
I came across a strange problem. Bringing it to its simpliest version I got the situation as show below.
Detailed implementation:
The device is 10M08SAU169I7G (Quartus17.1 Lite). Alongside with logic I have output timing constraints as follows:
```tcl
derive_pll_clocks -create_base_clocks -use_net_name
derive_clock_uncertainty
create_generated_clock \
-name FPDL_GEN_CLK \
-source [get_pins {clk_buf_inst|clk_out_buf_inst|gpio_one_bit.i_loop[0].altgpio_bit_i|out_path_ddr.fr_out_data_ddio|clkhi}] \
[get_ports {PPCLK_B}]
set_output_delay -clock [get_clocks FPDL_GEN_CLK] -max 2.5 [get_ports {PVSYNC}]set_output_delay -clock [get_clocks FPDL_GEN_CLK] -min -2.5 [get_ports {PVSYNC}]
```
Only CLK_FPDL has location assignment, everything else is unconstrained.
Timing is not met (results below).
The question is why is the interconnect delay so high? How to deal with it?
The curious thing is, when I change output delay constraints clock to c0, the same interconnect is nearly 0.
yours sincerely
PF
The design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays.
Why huge clock skew you might ask? That's because this is a cross-clock transfer.
