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frycoo's avatar
frycoo
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Very high interconnect delay

Hello, I came across a strange problem. Bringing it to its simpliest version I got the situation as show below. Detailed implementation:   The device is 10M08SAU169I7G (Quartus1...
  • skyjuice's avatar
    skyjuice
    4 years ago

    The design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays.

    Why huge clock skew you might ask? That's because this is a cross-clock transfer.

skyjuice's avatar
skyjuice
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

The design has such a high interconnect delay is due to the huge clock skew. In order to meet hold time requirement, the router will need to add additional routing delays.

Why huge clock skew you might ask? That's because this is a cross-clock transfer.

  • frycoo's avatar
    frycoo
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello skyjuice,

    Thanks for putting me on the right tracks. Although I don't know about cross-clock transfer (could you possibly point me to some literature?). What I understand from your response is clock skew is so high, partially, due to use of DDIO buffer (which introduce additional delay to the required path). Removing it and modifying output delays to be referenced to FPGA pin solved the problem.

    Modified constraints:

    set_output_delay \
    -clock [get_clocks pll_quarterRes:pll0|altpll:altpll_component|pll_quarterRes_altpll:auto_generated|wire_pll1_clk[0]] \
    -reference_pin [get_ports PPCLK_B] \
    -max 2.5 [get_ports {PVSYNC}]
    #set_output_delay -clock [get_clocks FPDL_GEN_CLK] -min -2.5 [get_ports {PVSYNC}]
    set_output_delay \
    -clock [get_clocks pll_quarterRes:pll0|altpll:altpll_component|pll_quarterRes_altpll:auto_generated|wire_pll1_clk[0]] \
    -reference_pin [get_ports PPCLK_B] \
    -min -2.5 [get_ports {PVSYNC}]