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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog

in verilog, how to do like q <= d[count:0]? reg [3:0] count; thanks
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The error message means that you are not allowed to use your output hazard in more than one always block.There´s the same problem with your reg sample. Try to fix that first, maybe there are some more problems.