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Altera_Forum's avatar
Altera_Forum
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14 years ago

verilog syntax problem

Having been using VHDL for a long time I am struggling with a bit of verilog that my books alone cannot help me translate 

 
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1);

Does the above statement mean that

GATE_BOARD_DQS_DELAY is assigned to 0 or 1 depending on RTL_DELAYS ??

What does the pound sign mean here? 

 
 
wire# ((CLOCK_TICK_IN_PS / 4) * 3 * 1) clk_shifted;

The other statement I am confused with is 

 
wire dm;

couldn't we just divide by 16?

Thank you all big time!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    1) Almost. GATE_BOARD_DQS_DELAY is assigned to 0 or BOARD_DQS_DELAY depending on RTL_DELAYS.

    2) It means that the expression that follows is the delay of the wire being declared. It probably won't synthesize in Quartus.

    3) You could. Looks like just a style choice on the part of the author.